1. Field of the Invention
The present invention relates to semiconductor packages and fabrication methods thereof, and more particularly, to a semiconductor package with a stacked structure and a fabrication method thereof.
2. Description of Related Art
Currently, electronic products are developed towards miniaturization, high electrical performance, multi-functionality and high speed. Accordingly, semiconductor packages are required to have such features as, small size, high electrical performance, multi-functionality, and high speed, to meet the requirement of electronic products.
Flip-chip technologies facilitate the reduction of chip packaging sizes and signal transmission paths and therefore have been widely used for chip packaging. Various types of packages such as chip scale packages (CSPs), direct chip attached (DCA) packages and multi-chip module (MCM) packages can be achieved through flip-chip technologies.
Further, chip stacking technologies have been developed to reduce the size of semiconductor packages and improve the functionality of semiconductor packages. However, warpage caused by thermal stresses can easily happen to such a semiconductor package. On the other hand, when such a semiconductor package is bonded to a packaging substrate through a plurality of conductive bumps, there are thermal stresses on the conductive bumps or lead so as to result in poor electrical joints between the semiconductor package and the packaging substrate.
FIGS. 1A to 1C are schematic cross-sectional views illustrating a semiconductor package and a fabrication method thereof according to the prior art.
Referring to FIG. 1A, a semiconductor wafer 10 having a first surface 10a and a second surface 10b opposite to the first surface 10a is provided. The semiconductor wafer 10 has a plurality of semiconductor chips 10′ and each of the semiconductor chips 10′ has a plurality of conductive posts 10c formed therein. A plurality of connection units 11 are formed on the first surface 10a of the semiconductor wafer 10 corresponding to the semiconductor chips 10′. Each of the connection units 11 has a first surface 11a, a second surface 11b opposite the first surface 11a, and a plurality of first conductive through holes 11c penetrating the first surface 11a and the second surface 11b and electrically connected to the conductive posts 10c of the corresponding semiconductor chip 10′ through a plurality of first conductive elements 12.
Further, a plurality of semiconductor chips 14 are formed on the first surfaces 11a of the connection units 11 through bottom surfaces 14a thereof and electrically connected to the connection units 11 through a plurality of second conductive elements 13. Furthermore, an encapsulant 15 is formed on the first surface 10a of the semiconductor wafer 10 for encapsulating the connection units 11, the semiconductor chips 14, the first conductive elements 12 and the second conductive elements 13.
Referring to FIG. 1B, continued from FIG. 1A, the second surface 10b of the semiconductor wafer 10 is ground to expose one ends of the conductive posts 10c and a redistribution layer 16 is formed on the second surface 10b of the semiconductor wafer 10. As such, the semiconductor wafer 10 and the redistribution layer 16 form an RDL (redistribution layer) structure. Further, a plurality of conductive bumps 17 are formed on the redistribution layer 16.
Referring to FIG. 1C, continued from FIG. 1B, a singulation process is performed to form a plurality of semiconductor packages. Further, such a semiconductor package is disposed on a top surface 18a of a substrate 18 through the conductive bumps 17, and a plurality of solder balls 17′ are formed on a bottom surface 18b of the substrate 18.
In the above-described method, thermal stresses easily occur in a high temperature process so as to cause warpage of the RDL structure and the connection units. As such, portions of the first conductive elements fail to electrically connect the connection units and the RDL structure and portions of the second conductive elements fail to electrically connect the semiconductor chips and the connection units, thus resulting in an electrical connection failure among the semiconductor chips, the connection units and the semiconductor wafer.
Therefore, there is a need to provide a semiconductor package and a fabrication method thereof to overcome the above-described disadvantages.